On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

On ATPG for Multiple Aggressor Crosstalk Faults in Presence of Gate Delays Abstract

Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk noise on a net, it may not be possible to activate all aggressors logically or simultaneously. Therefore, pattern generation must focus on activating a maximal subset of aggressors switching around the same time the victim net switches. This is a well-known problem. In this paper, we present a novel solution assuming a unit delay model for the gates, combining 0-1 Integer Linear Program (ILP) with traditional stuck-at fault ATPG. The maximal aggressor activation is formulated as a linear programming problem while the fault effect propagation is treated as an ATPG problem and the gate delays are subsumed by a circuit transformation. The proposed technique was applied to ISCAS 85 benchmark circuits. Results indicate that percentage of total capacitance that can be switched varies from 30-80%. 1

A Study on Impact of Leakage Current on Dynamic Power

Abstract — Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now become comparable to the switching current. Traditionally, dynamic power and leakage power are computed separately. Dynamic power computation does not include leakage from nonswitching nodes. In this paper, we show that in upcoming 45nm technology, leakage from non-switching nodes can account for as much as 38 % of total dynamic current. Hence leakage from nonswitching nodes can not be neglected during dynamic power computation. To facilitate this study on large benchmark circuits on which spice level simulation is impractical, we created a compact simulation model for modeling various pattern dependent leakage currents to allow leakage computation at gate level. Using a simulation based experiment we compare leakage and switching currents on ISCAS-85 benchmark circuits. The experiments are based on Berkeley Predictive Technology Model for 45nm technology. The results firmly establish the need to consider leakage from non-switching nodes during dynamic power computation. I

Floreon+ Modules: A Real-World HARPA Application in the High-End HPC System Domain

reserved9siThis chapter is centered around uncertainty computation with on-demand resource allocation for run-off prediction in a High-Performance Computer environment. Our research stands on a runtime operating system that automatically adapts resource allocation with the computation to provide precise outcomes before the time deadline. In our case, input data comes from several gauging stations, and when newly updated data arrives, models must be re-executed to provide accurate results immediately. Since the models run continuously (24/7), their computational demand is different during various hydrological events (e.g. periods with heavy rain and without any rain) and therefore computational resources have to be balanced according to the event severity. Although these kinds of models should run constantly, they are very computationally demanding during discrete periods of time, for example in the case of heavy rain. Then, the accuracy of the results must be as close as possible to reality. The work relies on the HARPA runtime resource manager that adapts resource allocation to the runtime-variable performance demand of applications. The resource assignment is temperature-aware: the application execution is dynamically migrated to the coolest cores, and this has a positive impact on the system reliability.mixedAntoni Portero, Radim Vavrik, Martin Golasowski, Jiri Sevcik, Giuseppe Massari, Simone Libutti, William Fornaciari, Stepan Kuchar, Vit VondrakPortero, Antoni; Vavrik, Radim; Golasowski, Martin; Sevcik, Jiri; Massari, Giuseppe; Libutti, Simone; Fornaciari, William; Kuchar, Stepan; Vondrak, Vi